Method of fabricating integrated circuit with improved yield rat

Details Method of fabricating integrated circuit with improved yield rat Method of fabricating integrated circuit with improved yield rat

1994-03-03

1995-08-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 51, 437923, H01L 2166, G01R 3126

Patent

active

054440009

ABSTRACT:
A method of fabricating semiconductor integrated circuits with an improved yield rate is realized, which requires no special circuits for selecting normal circuit blocks. Removable temporary wires are connected to circuit blocks, which are thus tested. After removing the temporary wires, a plurality of normally-operating circuit blocks are interconnected by new main wires. The need of a special selecting circuit for replacing defective circuit blocks with normal circuit blocks is eliminated without increasing the delay time due to redundancy. The freedom of the main wiring formed after removal of the temporary wires is so high that the functional freedom of the system constructed is improved.

REFERENCES:
patent: 4415606 (1983-11-01), Cynkar et al.
patent: 5139963 (1992-08-01), Suzuki
Wolf, Silicon processing for the VLSI ERA vol. 2 pp. 189-199 and 244-251.

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