Modified poly-buffered isolation

Details Modified poly-buffered isolation Modified poly-buffered isolation

1997-02-11

1999-11-02

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257506, H01L 2900

Patent

active

059776080

ABSTRACT:
A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask. The oxidation mask includes exposed regions (210) of the oxide layer (120) where field isolation oxide regions (300) will be formed therein.

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Guldi, R.L. et al., "Characterization of Poly-Buffered LOCOS in Manufacturing Environment," 1989, J. Electrical, Soc., vol. 136, No. 12, pp. 3815-3820.

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