Boots – shoes – and leggings
Patent
1982-06-28
1984-11-27
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1516
Patent
active
044854382
ABSTRACT:
In the operation of a network of data processing units, a method and apparatus for transferring information between units in a multi-processor environment at high throughput rates.
The high throughput rates are achieved by concurrent send/receive direct-memory-access transfers between buffer memories associated with each unit. The invention provides for direct-memory-access (DMA) transfers between a buffer memory and the data port of the sending unit and direct-memory-access transfers between this data port and the buffer memory of the receiving unit; thus eliminating shared-memory resource allocation, memory access arbitration and other programmed operations which normally require execution of several instructions by each unit's processor for each transfer.
Each unit interfaces with the system bus through a message transfer facility which groups the buffer memory, the output data port, an attention identification register, resident traffic control DMA and data processors and optional miscellaneous function expansion.
Each message transfer is initiated by the sending unit placing on the system bus the address of the targeted receiving unit attention identification register, and the sending unit unique identification. The receiving unit, upon recognizing the identification code in its attention register, initiates the direct-memory-access transfer.
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Intel, Section 2, "Functional Description," pp. 2-1 to 2-17.
Intel, Section 5, "Design Guidelines and System Applications," pp. 5-1 to 5-32.
Myrmo Erik R.
Wells Michael F.
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