Process for DRAM capacitor formation

Details Process for DRAM capacitor formation Process for DRAM capacitor formation

1997-11-21

1999-11-02

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

438697, 438704, 438723, 438724, H01L 218242

Patent

active

059769777

ABSTRACT:
A DRAM capacitor is formed using a process that avoids high temperature processing steps and which emphasizes low cost processes. An interlayer dielectric, typically CVD TEOS oxide, is provided over the transfer FET and bit line contact of the DRAM cell. The interlayer dielectric is planarized and an etch stop layer is provided over the planarized surface of the etch stop layer. A contact via is formed to expose a source/drain region for the transfer FET. Doped polysilicon is provided to fill the contact via and to form a first layer of doped polysilicon over the etch stop layer. The first polysilicon layer is patterned to form a plate aligned over the contact via using a first photoresist mask and etching. The first photoresist mask is left in place over the plate and a first layer of selective oxide is deposited over the etch stop layer so that the first selective oxide layer does not deposit over the photoresist mask. The first photoresist mask is then removed to expose the surface of the plate and a second doped polysilicon layer is provided over the first selective oxide layer and in contact with the first polysilicon plate. A second photoresist mask is provided over the second polysilicon layer and the second polysilicon layer is etched to define fins extending upward and outward from the first polysilicon plate. This process is repeated to form as complex of a structure for the lower capacitor electrode as is desired.

REFERENCES:
patent: 5429956 (1995-07-01), Shell et al.
patent: 5491103 (1996-02-01), Ahn et al.
patent: 5514247 (1996-05-01), Shan et al.

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