Method of making self-aligned GaAs/AlGaAs FET's

Details Method of making self-aligned GaAs/AlGaAs FET's Method of making self-aligned GaAs/AlGaAs FET's

1989-06-27

1990-05-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437 41, 437126, 437203, 437228, 357 15, H01L 21338

Patent

active

049277820

ABSTRACT:
A method of making a self-aligned FET includes the following steps. First, selectively doped heterostructure substrate having a predetermined crystalline structure is obtained having a heavily doped top GaAs layer, having a heavily doped AlGaAs layer under the top layer that is resistant to orientation-dependent etching, and having an undoped underlying AlGaAs layer and an undoped bottom GaAs layer. Then, an uppermost GaAs layer is deposited on the top layer. Then, an angular recess is etched through the uppermost GaAs layer and through the top heavily doped GaAs layer of the heterostructure substrate with an orientation-dependent etchant down to the etch resistant AlGaAs layer, whereby the length of the angular recess is wider at the base of the recess than at the top of the recess because of the predetermined crystalline structure and the orientation-dependent etchant. Next, a refractory metal gate of tantalum silicide is deposited in the recess. The length of the refractory metal gate is substantially the same as the length of the top of the recess and is aligned therewith. The refractory metal gate is then covered with an etch resistant polyimide material. By subsequent steps including etching, source and drain implantation, and deposition of metal contacts, the fabrication of the self-aligned FET is completed.

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