Method of making a MOS transistor

Fishing – trapping – and vermin destroying

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437 34, 437 41, 437 57, 437 28, 437233, 437186, 437192, 437200, 357 233, H01L 21265

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049277774

ABSTRACT:
A method of making a MOS transistor having source and drain extensions includes forming on a surface of a substrate of single crystalline silicon a gate line having a thin layer of silicon oxide between the gate line and the substrate surface. A light dose of ions of a desired conductivity type are embedded in the substrate surface at each side of the gate line up to the side walls of the gate line. Spacers of thermally grown silicon oxide are formed on the side walls of the gate line and a dose of the ions of the desired conductivity type are embedded into the substrate surface at each side of the gate line to form source and drain regions. The source and drain regions extend up to the spacers and have lightly doped extensions extending up to the side walls of the gate line under the spacers.

REFERENCES:
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4503601 (1985-03-01), Chiao
patent: 4514897 (1985-05-01), Chiu et al.
patent: 4616399 (1986-10-01), Ooka
patent: 4701423 (1987-10-01), Szluk
Bassous et al., "Self-Aligned Polysilicon Gate MOSFETs with Tailored Source and Drain Profiles", IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1980, pp. 5146-5147.
Wang, "Lithographically Defined Self-Aligned Double-Implanted Doped FET Device", IBM Technical Disclosure Bulletin, vol. 27, No. 8, Jan. 1985, pp. 4629-4631.

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