Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1997-09-16
1999-03-23
Nguyen, Tan T.
Static information storage and retrieval
Addressing
Plural blocks or banks
365 63, G11C 506
Patent
active
058869433
ABSTRACT:
An increase in a dynamic random access memory (DRAM) chip area is minimized by dividing data lines into multiple sections, arranging global data lines parallel to the data lines and placing them in a hierarchical structure. The switches connecting the data lines and the global data lines are arranged separately or in alternate positions to further reduce the chip area. The influence of noise due to the length of data lines is reduced. Sense amplifier drive circuits are controlled to selectively apply voltages to the sense amplifiers depending upon the length of the path from each sense amplifier to a particular memory cell.
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Itoh Kiyoo
Sekiguchi Tomonori
Hitachi , Ltd.
Nguyen Tan T.
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