N-Channel JFET device having a buried channel region, and method

Details N-Channel JFET device having a buried channel region, and method N-Channel JFET device having a buried channel region, and method

1981-10-05

1983-09-27

Edlow, Martin H.

357 41, H01L 2918

Patent

active

044070055

ABSTRACT:
A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface of the body outside the p-well. A buried channel connects the source and drain. A p-layer above the buried channel forms the top gate. Gate leakage current and noise are very low.

REFERENCES:
patent: 4314267 (1982-02-01), Bergeron et al.
patent: 4322738 (1982-03-01), Bell

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