Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Patent
1980-07-11
1984-11-27
Anagnos, Larry N.
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
307270, 330267, 331116FE, H03F 316, H03F 326
Patent
active
RE0317497
ABSTRACT:
A complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, the gate of the two FETs being applied with a common linear input, respective load resistors connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs, and a bias resistor connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.
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Kalin, "Proceedings of the National Electronic Conference"; vol. 28, Oct. 8-10, 1973, Oakbrook (U.S.) pp. 368-372.
Electronics & Nucleonics Dictionary-Markus, 1966, pp. 106-107, 3rd Ed., Group A.U. 252.
Anagnos Larry N.
Hitachi , Ltd.
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