Multiplex communications – Wide area network – Packet switching
Patent
1985-04-29
1987-07-21
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
375111, H04J 306
Patent
active
046823271
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a polyphase phase-locked oscillator in which a plurality of signal channels with some phase difference are transmitted with time division multiplex system, and a reception side receives the particular channel signal with phase synchronization.
When a sampling clock is to be derived in a time division multiplex transmissiion line in which a plurality of channel signals are multiplexed with some phase difference, the clock signal with the phase locked with the signal channel having high mark ratio is obtained. Accordingly, it has the disadvantage that the margin for recognition in other signal channels is decreased. The present invention provides a sampling clock signal locked with each signal channels so that the recognition margin is increased.
BACKGROUND OF THE INVENTION
A new kind of transmission system in which a plurality of signal channels are multiplexed with some phase difference is considered as a subscriber transmission system in an Integrated Service Digital Network (ISDN). In the ISDN transmission system, a bus line system between a digital service unit as a master station and a terminal apparatus as a slave station is considered promising in the number of necessary lines, the simple process for expanding, and less quantity of necessary hardware.
FIG. 1 shows a subscriber coupling system with a bus line schematically. In the figure, the numeral 1 is a digital service unit (DSU), 2-1 through 2-N are n number of terminal apparatuses, 3 is a T line (transmission line), 4 is an R line (reception line), 5 is a termination circuit. As shown, a plurality of terminal apparatuses are coupled with one another in a bus line. The T line and the R line show bus lines, and the R line is directed from the DSU to each terminal apparatuses, and the T line is directed from each terminal apparatuses to the DSU.
In a bus system for subscriber system, a simple bus system as shown in FIG. 2A (length between DSU and DT.sub.1 is 0, and the length between DT.sub.1 and DT.sub.n is about 100 m), an extended bus system as shown in FIG. 2B (the length between DSU and DT.sub.1 is about 500 m, and the length between DT.sub.1 and DT.sub.n is about 30 m), and a point-to-point system as shown in FIG. 2C (length between DSU and DT.sub.1 is longer than 1000 m) are three typical ones. In FIGS. 2A through 2C, the same reference numerals as those of FIG. 1 show the same members.
The phase lock operation between a transmission side and a reception side in FIGS. 2A through 2C has been carried out as described below.
The DSU transmits a data to an R line like a broadcasting manner, and each subscriber apparatus derives clock component in reception data train for phase lock purposes. However, the reception phase at the DSU through the T line is not uniform, because the length between the DSU and each terminal apparatus differs for each terminal apparatus. Of course, it is preferable that a common DSU is used for the systems of FIGS. 2A through 2C. Accordingly, a 100% AMI code is used as a transmission code, and each terminal apparatus transmits not only an information data but also a frame bit which indicates the beginning of a frame, so that the DSU may derive a sampling clock by a conventional phase lock circuit.
FIG. 3 shows the configuration of a prior digital phase lock circuit. In the figure, the numeral 6 is a binary level quantized phase comparator, 7 is a sequential loop filter, 8 is a fixed oscillator, 9 is a circuit for pulse add and/or pulse delete, and 10 is a frequency divider. In FIG. 3, the phase comparator 6 compares the phase of an input signal with the output signal phase for every input bit, and provides output as +1 or -1, which is applied to the sequential loop filter 7 for improving the control reliability to control the circuit 9. The sequential loop filter 7 is usually composed of an up/down counter which is incremented by +1 input signal and is decremented by -1 input signal. The up/down counter provides an output signal when the content of the up/down
REFERENCES:
patent: 3597552 (1971-08-01), Goto
patent: 4189622 (1980-02-01), Foshee
patent: 4290135 (1981-09-01), Zemanek
patent: 4566099 (1986-01-01), Magerl
Hayashi Kazuhiro
Okumura Yasuyuki
Chin Wellington
Nippon Telegraph and Telephone Corp.
Olms Douglas W.
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