Arrangement for checking the parity of parity-bits containing bi

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371 68, G06F 1110

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046988149

ABSTRACT:
A logic circuit for checking the parity of many bit groups simultaneously and jointly. The parity bits generated by the parity generators are interchanged crosswise, combined with the parity bits contained in the bit groups and applied to a single common output terminal. Consequently, only one specific output must be checked. The checking circuit itself is checked by inverting one of the parity generators periodically.

REFERENCES:
patent: 3245049 (1966-04-01), Sakalay
patent: 3602886 (1971-08-01), Carter
patent: 3732407 (1973-05-01), Brewster
patent: 3825894 (1974-07-01), Johnson
patent: 3914741 (1975-10-01), Bonser
patent: 4483003 (1984-11-01), Beal
L. J. Kobesky "Diagnostic Parity Error Forcing Mechanism" Vol. 19, No. 3, 8/1876, p. 853.
K. Low "Shared Parity Checker" Vol. 11, No. 7, 12/1968, pp. 882-883, both from IBM Tech. Disclosure Bulletin.

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