Logarithmic arithmetic logic unit

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364754, 364761, 364715, G06F 7556, G05F 750

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active

046823026

ABSTRACT:
In a digital signal processing system, a logarithmic arithmetic logic unit is provided which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation is provided. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range is provided.

REFERENCES:
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patent: 4555768 (1985-11-01), Lewis, Jr. et al.
E. Hall et al., "Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications" IEEE Trans. On Comp. 2/1970, pp. 97-105.
J. Mitchell, Jr., "Computer Multiplication and Division Using Binary Logarithms" IRE Trans. on Electronic Computer, Aug. 1962, pp. 512-517.
T. Brubaker et al., "Multiplication Using Logarithms Implemented With Read-Only Memory", IEEE Trans. on Comp. vol. C-24, No. 8, 8/1975, pp. 761-765.
J. Lang et al., "Integrated-Circuit Logarithmic Arithmetic Units" IEEE Trans. on Comp., vol. C-34, No. 5, May 1985, pp. 475-483.
Sofer et al., Parallel Pipeline Organization of Execution Unit, IBM Tech. Disclosure Bull., vol. 14, No. 10, Mar. 1972, pp. 2930-2933.
Kingsbury et al., Digital Filtering Using Logarithmic Arithmetic, Electronics Letters, vol. 7, No. 2, Jan. 28, 1971, pp. 56-58.

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