Output control circuit to prevent output of initial spike noise

Details Output control circuit to prevent output of initial spike noise Output control circuit to prevent output of initial spike noise

1985-05-20

1987-10-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307550, 307568, 307200B, 307594, 307592, H03B 104, H03K 500, H03K 513

Patent

active

046985298

ABSTRACT:
Initial spike noise which occurs, when an IC is switched on, is suppressed by an output control circuit provided between the output terminal of an inner logic circuit and an output circuit of the IC. The output control circuit clamps the input terminal of the output control circuit until the supply voltage builds up to a steady state. The output control circuit comprises two stages each connected between the supply voltage and ground. The first stage has a series connection of a first FET and first resistor, the second stage has a series connection of a second FET, third FET and second resistor. The first FET is controlled by a reset signal and turns off the second FET until the reset signal is released. The second FET turns off the third FET which transmits the output signal of the inner circuit to the output circuit of the IC. When the reset signal is released, the third FET and hence the output circuit begins operation.

REFERENCES:
patent: 3774053 (1973-11-01), Carlson
patent: 3975649 (1976-08-01), Kawagoe et al.
patent: 4019070 (1977-04-01), Sakaguchi et al.
patent: 4044270 (1977-08-01), Lesser
patent: 4345172 (1982-08-01), Kobayashi et al.
IBM Technical Disclosure Bulletin, vol. 20, No. 6, Nov., 1977, pp. 2370-2371, New York, U.S.; C. R. Hoffman, "Anti-Glitch Circuit".

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