Method of formation of transistor and logic gates

Details Method of formation of transistor and logic gates Method of formation of transistor and logic gates

1993-01-11

1994-05-03

Thomas, Tom

Fishing, trapping, and vermin destroying

437 51, 437 56, 437 89, 437915, H01L 2170

Patent

active

053087780

ABSTRACT:
A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with multiple inputs.

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