Floating point register alias table FXCH and retirement floating

Details Floating point register alias table FXCH and retirement floating Floating point register alias table FXCH and retirement floating

1993-09-30

1996-03-12

Whitfield, Michael A.

Boots, shoes, and leggings

395375, 395800, 364DIG1, G06F 1202, G06F 930, G06F 1531

Patent

active

054993520

ABSTRACT:
A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As a set of uops is presented to the floating point RAT logic, their logical sources are used as indices into a floating point RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical sources is found. An efficient FXCH operation is implemented within the floating point RAT mechanism by switching 6-bit physical register pointers rather than switching the actual data for each physical register which is 86-bits wide. There is a retirement floating point RAT array with dual valid bits and a dual TOS pointer to account for speculative FXCH operations in addition to another floating point RAT array. The retirement floating point RAT array is updated only upon uop retirement whereas the floating point RAT array is updated at uop issuance.

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Popescu, et al., "the Metaflow Architecture," IEEE Micro, Jun. 1991, pp. 10-13, 63-73.

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