Planarized trench and field oxide isolation scheme

Details Planarized trench and field oxide isolation scheme Planarized trench and field oxide isolation scheme

1995-11-29

1997-11-25

Fourson, George R.

Fishing, trapping, and vermin destroying

437924, H01L 2176

Patent

active

056912323

ABSTRACT:
An isolation method for separating active regions in a semiconductor substrate by combining field oxide formation with trench isolation is disclosed. Deep trenches are etched in a silicon substrate. An oxide layer is deposited over the entire substrate such that the oxide layer also fills the trenches that have been etched. Next, a layer of polysilicon is deposited over the wafer and etched back to form polysilicon spacers. These polysilicon spacers are used to align a photoresist mask that is used to etch the oxide overlying the active regions of the substrate, thereby resulting in fully planarized isolation regions with fully walled active regions.

REFERENCES:
patent: 4472240 (1984-09-01), Kameyama
patent: 5385861 (1995-01-01), Bashir et al.
Kurosawa et al. A New Bird's Beak Free Field Isolation Technology for VLSI Devices, International Electron Devices Meeting, Dig. Tech., Paper, pp. 384-387 (1981).
Rung et al., Deep Trench Isolated CMOS Devices, International Electron Devices Meeting, Digest Technical Paper, pp. 237-240 (1982).
Katsumata et al., Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage, ESSDERC, pp. 133-136 (Sep. 1983).
Lutze et al., Electrical Characteristics of Advanced LOCOS Isolation for Deep Submicrometer CMOS, IEEE Transactions on Electron Devices, vol. 38, No. 2, pp. 242-245 1991.
Poon et al., A Trench Isolation Process for BiCMOS Circuits, IEEE Bipolar Circuits and Technology Meeting 3.3, pp. 45-48 1993.
Kwasnick R.F. et al., "Buried-Oxide Isolation With Etch-Stop (Boxes)", IEEE Electron Device Letters, vol. 9, No. 2, Feb. 1988, pp. 62-64.

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