Synchronous semiconductor memory device allowing control of oper

Details Synchronous semiconductor memory device allowing control of oper Synchronous semiconductor memory device allowing control of oper

1999-05-06

2000-09-26

Phan, Trong

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523008, G11C 800

Patent

active

061250783

ABSTRACT:
For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.

REFERENCES:
patent: 5384735 (1995-01-01), Park et al.
patent: 5497355 (1996-03-01), Mills et al.
patent: 5892730 (1999-04-01), Sato et al.
patent: 5923613 (1999-07-01), Tien et al.
patent: 5991232 (1999-11-01), Matsumura et al.

Affiliated with

Also associated with

Rating

Synchronous semiconductor memory device allowing control of oper does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous semiconductor memory device allowing control of oper, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous semiconductor memory device allowing control of oper will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2105985