Semiconductor memory device having multiple global I/O line pair

Details Semiconductor memory device having multiple global I/O line pair Semiconductor memory device having multiple global I/O line pair

1999-04-01

2000-09-26

Phan, Trong

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, 365 63, 365207, G11C 800

Patent

active

061250708

ABSTRACT:
In a DRAM, many global I/O line pairs extend on memory cell arrays between sub-word driver regions or word line shunt regions. Local I/O line pairs are arranged on sense amplifier regions divided correspondingly to memory sub-blocks, respectively. Switching elements connecting the global I/O line pairs and local I/O line pairs are dispersed on the sense amplifier regions. A plurality of bit lines are commonly connected to each local I/O line pair. Therefore, the DRAM allows input/output of data of multiple bits while suppressing decrease in operation speed and increase in power consumption.

REFERENCES:
patent: 5781495 (1998-07-01), Arimoto
patent: 5867439 (1999-02-01), Asakura
patent: 5953257 (1999-09-01), Inoue et al.
patent: 5966340 (1999-10-01), Fujino et al.
"a 286mm2 256Mb DRAM with X32 Both-Engs DQ", by Watanabe et al., 1995 Symposium on VLSI Circuits Digest of Technical Papers, pp. 105-106.

Affiliated with

Also associated with

Rating

Semiconductor memory device having multiple global I/O line pair does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having multiple global I/O line pair, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having multiple global I/O line pair will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2105872