Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-08-26
2000-09-26
Nguyen, Viet Q.
Static information storage and retrieval
Floating gate
Particular biasing
36518533, 3651851, 36518518, 36518501, 365218, G11C 1604
Patent
active
061250600
ABSTRACT:
A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.
REFERENCES:
patent: 5280446 (1994-01-01), Ma et al.
patent: 5343424 (1994-08-01), Chang et al.
patent: 5739567 (1998-04-01), Wong
patent: 5879992 (1999-03-01), Hsieh et al.
patent: 5991204 (1999-11-01), Chang
U.S. application No. 09/072,924, Chang, filed May 5, 1998.
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