Protection circuit

Details Protection circuit Protection circuit

1995-05-30

1996-03-12

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361 91, 257355, H02H 320

Patent

active

054991528

ABSTRACT:
Independently of a punch-through MOS transistor Q.sub.3 used as an I/O protection element in which the drain is connected to an input node or output node and the source is connected to a GND or Vcc, an element for-setting the gate of punch-through MOS transistor Q.sub.3 to the GND potential is provided so that its operating speed may be slower than the punch-through speed of the punch-through MOS transistor Q.sub.3. In consequence, a high surge applied from I/O terminal can be punched through before the gate insulating film of the punch-through transistor Q.sub.3 undergoes a high electric field, to thereby protect the gate insulating film.

REFERENCES:
patent: 4739438 (1988-04-01), Sato
patent: 4937700 (1990-06-01), Iwahashi
patent: 5086365 (1992-02-01), Lien
patent: 5121179 (1992-06-01), Sasaki

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