Virtual addressing for I/O adapters

Details Virtual addressing for I/O adapters Virtual addressing for I/O adapters

1978-10-23

1980-10-14

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 300

Patent

active

042285046

ABSTRACT:
In a paged, virtual memory computer system, apparatus is provided for enabling I/O adapters to use virtual addresses. After each I/O data transfer, the main memory address involved in the transfer is incremented. This address is maintained in an I/O register associated with the I/O adapter performing the transfer. If a page boundary is crossed in the process of incrementing, the channel forms an I/O event indicating the page crossing and calling for translation of the incremented address. When the I/O adapter involved in the page crossing attempts a further data transfer, the channel disconnects the I/O adapter. The channel holds the I/O adapter disconnected until the page crossing denoted by the I/O event has been resolved by translating the incremented address and providing a new main memory address for continuing the data transfer. Because the disconnect is effected by ignoring the priority of the disconnected adapter when it requests service, other adapters of lower priority can be serviced by the channel during the disconnect. When completion of the address translation is signalled, the I/O adapter is no longer held disconnected.

REFERENCES:
patent: 3675209 (1972-07-01), Trost et al.
patent: 3704453 (1972-11-01), Blackwell et al.
patent: 3839706 (1974-10-01), Borchsenius
patent: 3898623 (1975-08-01), Cormier
patent: 3947823 (1976-03-01), Padegs et al.

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