Submicron channel length MOS inverter with depletion-mode load t

Details Submicron channel length MOS inverter with depletion-mode load t Submicron channel length MOS inverter with depletion-mode load t

1979-02-12

1980-10-14

Wojciechowicz, Edward J.

357 23, 357 41, 357 46, 357 55, 357 56, H01L 2702

Patent

active

042284473

ABSTRACT:
An improved, high speed n-channel MOS inverter structure including a self-aligned silicon gate depletion-mode load device integrated in series with a nonplanar, submicron channel enhancement-mode switching transistor. The enhancement-mode switching device is formed on a field of the substrate that includes an elevated, plateau region joined to a surrounding planar area by a slope. The MOS load transistor is formed on an adjoining planar portion of the surface. The process for fabricating the devices features successive ion implation of boron and arsenic through an oxide layer that includes a smoothly tapered "beak" formed by a local oxidation technique.

REFERENCES:
patent: 3823352 (1974-07-01), Pruniaux et al.
IEEE J. Solid State Cir., vol. SC-11, No. 4, Aug. 1976, pp. 443-452, Lin et al.
Research and Education Assn., N. Y. (1972), p. 602, Fogiel.

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