Shared-sense amplifier control signal generating circuit in dyna

Details Shared-sense amplifier control signal generating circuit in dyna Shared-sense amplifier control signal generating circuit in dyna

1990-11-20

1993-11-30

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365149, 365208, G11C 1134

Patent

active

052672140

ABSTRACT:
A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.

REFERENCES:
patent: 4241425 (1980-12-01), Cenker et al.
patent: 4351034 (1982-09-01), Eaton, Jr. et al.
patent: 5014246 (1991-05-01), Komatsu et al.
patent: 5016224 (1991-05-01), Tanaka et al.

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