Fail-safe method to read a timer which is based on a particular

Details Fail-safe method to read a timer which is based on a particular Fail-safe method to read a timer which is based on a particular

1996-04-17

1997-12-30

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Determining machine or apparatus operating time or...

G07C 302

Patent

active

057039194

ABSTRACT:
A method and apparatus for reading a timer with an asynchronous circuit. A computer system is provided having a system clock and an asynchronous timer clock. The computer system includes a counter clocking from the timer clock and a latch coupled to output of the counter. First logic, synchronized to the timer clock, is coupled to control the latch responsive to a control signal from the computer system. Second logic synchronized to the system clock and coupled to the first logic is configured to provide an indication to the computer system of when the system can read the latched data and be assured of its validity. The computer system will thereby be prevented from reading the timer before it has stabilized.

REFERENCES:
IBM Tech Disc. Bul. vol. 26 No. 3A Aug. 1983 "Program Status Latch" Crosthwait et al.

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