Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1997-10-08
2000-09-26
Cain, Edward J.
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438710, 438711, 438714, H01L 21302
Patent
active
061242128
ABSTRACT:
A method for forming a patterned polysilicon layer within a microelectronics fabrication. There is first provided a substrate layer employed within a microelectronics fabrication. There is then formed upon the substrate layer a blanket polysilicon layer. There is then formed upon the blanket polysilicon layer a blanket organic polymer layer. There is then formed upon the blanket organic polymer layer a patterned photoresist layer, where the patterned photoresist layer has a high areal density region and a low areal density region. There is then etched through a first plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket organic polymer layer to form a patterned organic polymer layer while reaching the blanket polysilicon layer. The patterned organic polymer layer has a high areal density region corresponding with the high areal density region of the patterned photoresist layer and a low areal density region corresponding with the low areal density region of the patterned photoresist layer. The blanket polysilicon layer also has formed thereupon an organic polymer residue layer within portions of the low areal density region of the patterned organic polymer layer. The first plasma etch method employs a first etchant gas composition comprising an oxygen containing species, a nitrogen containing species and a bromine containing species. There is then etched through a second plasma etch method while employing at least the patterned organic polymer layer as an etch mask layer the blanket polysilicon layer to form the patterned polysilicon layer, while suppressing a micro-loading effect.
REFERENCES:
patent: 4948462 (1990-08-01), Rossen
patent: 5198384 (1993-03-01), Dennison
patent: 5254213 (1993-10-01), Tamaki
patent: 5269879 (1993-12-01), Rhoades et al.
patent: 5427963 (1995-06-01), Richart et al.
patent: 5449639 (1995-09-01), Wei et al.
patent: 5817562 (1998-10-01), Chang et al.
patent: 5895239 (1999-04-01), Jeng et al.
Fan Yuh-Da
Fang Weng-Liang
Ackerman Stephen B.
Cain Edward J.
Saile George O.
Taiwan Semiconductor Manufacturing Co.
LandOfFree
High density plasma (HDP) etch method for suppressing micro-load does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High density plasma (HDP) etch method for suppressing micro-load, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density plasma (HDP) etch method for suppressing micro-load will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2099820