Process of fabricating semiconductor device having flattening st

Details Process of fabricating semiconductor device having flattening st Process of fabricating semiconductor device having flattening st

1995-04-24

1996-03-12

Quach, T. N.

Fishing, trapping, and vermin destroying

437228, 437978, 1566361, H01L 21302

Patent

active

054985749

ABSTRACT:
An upper portion of a silicon nitride layer deposited over a silicon oxide layer which in turn covers metal wirings is partially polished for forming a flat surface remaining silicon nitride layer prevents the metal wirings from a strong, corrosive cleaning solution during a cleaning stage of residual oxide particles and contaminant, and the remaining silicon nitride layer and a part of the silicon oxide layer are uniformly etched by dry etchant so as to decrease a parasitic capacitance coupled to the metal wirings.

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Wolf, S., et al., Silicon Processing, Lattice press, 1986, pp. 514-520, 547-556.

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