Method of fabricating memory cell for semiconductor integrated c

Details Method of fabricating memory cell for semiconductor integrated c Method of fabricating memory cell for semiconductor integrated c

1992-07-15

1996-03-12

Forson, George

Fishing, trapping, and vermin destroying

437 60, 437919, 216 6, 216 22, H01L 218242

Patent

active

054985617

ABSTRACT:
According to a method of fabricating a memory cell for a semiconductor integrated circuit, a lower electrode having a predetermined shape is formed on a semiconductor layer. A first insulating interlayer is formed on an entire surface of the semiconductor layer such that only a top surface of the lower electrode is exposed. A dielectric having a high dielectric constant is formed on the lower electrode and on the semiconductor layer. An upper electrode is formed on the dielectric having a high dielectric constant. The upper electrode constitutes a capacitor with the lower electrode through the dielectric.

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