Method for planarizing the surface of an integrated circuit over

Details Method for planarizing the surface of an integrated circuit over Method for planarizing the surface of an integrated circuit over

1992-05-11

1994-04-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437194, 437199, 437228, 156643, 156653, H01L 2144

Patent

active

053025512

ABSTRACT:
A method is provided for planarizing the surface of an integrated circuit over a metal interconnect layer. Metal interconnect lines and surrounding regions of a partially fabricated integrated circuit are first coated with a thin layer of dielectric substantially free of voids and then coated with a polysilicon layer. The polysilicon layer is planarized back to the level of the dielectric layer on top of the interconnects, providing a substantially planar surface for subsequent fabrication steps including deposition of a second dielectric layer and an overlying metal layer.

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