VLSI interconnect method and structure

Details VLSI interconnect method and structure VLSI interconnect method and structure

1990-05-29

1994-04-12

Quach, T. N.

Fishing, trapping, and vermin destroying

437192, 437200, 437190, 437 24, 437228, 156656, H01L 21283, H01L 21336

Patent

active

053025393

ABSTRACT:
A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoid shorting out devices. However, the present invention patterns this conductive layer, thereby providing a local interconnect with the sheet resistance of the order of one ohm per square. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect level fulfills all of the functions which a buried contact layer could fulfill, and fulfills other functions as well.

REFERENCES:
patent: 3879746 (1975-04-01), Fournier
patent: 4102733 (1978-07-01), De La Moneda et al.
patent: 4178605 (1979-12-01), Hsu
patent: 4253888 (1981-03-01), Kikuchi
patent: 4305200 (1981-12-01), Fu et al.
patent: 4314874 (1982-02-01), Abe et al.
patent: 4333226 (1982-06-01), Abe et al.
patent: 4378628 (1983-04-01), Levinstein et al.
patent: 4384301 (1983-05-01), Tasch, Jr. et al.
patent: 4392150 (1983-07-01), Courreges
patent: 4502209 (1985-03-01), Eizenberg et al.
patent: 4545116 (1985-10-01), Lau
patent: 4570328 (1986-02-01), Price et al.
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4593454 (1986-06-01), Baudrant et al.
patent: 4605947 (1986-08-01), Price et al.
patent: 4635347 (1987-01-01), Lien et al.
patent: 4652812 (1987-03-01), Gimpelson et al.
patent: 4674174 (1987-06-01), Kishita et al.
patent: 4675715 (1987-06-01), Lepselter et al.
patent: 4677735 (1987-07-01), Malhi
patent: 4804636 (1989-02-01), Groover, III et al.
Shatas, S., et al., Workshop on Refractory Metal Silicides, Continuing Education, University of California, Berkeley, Sep. 20-22, 1983, 20. pages.
Kern, W., et al., Chemical Etching, in Thin Film Process, (Vossen et al. ed.), Academic Press, 1978, pp. 401-411.
Alperin et al., IEEE Trans. Elec. Dev., ed-32 (2), Feb. 1985, pp. 141-149.
Ting, C. Y., "Tin formed by Evaporation . . . ," J. Vac. Sci. Technol. 21(1), May/Jun. 1982, pp. 14-18.
Ting, C. Y., "Silicide for Contacts . . . , " IEEE IEDM 1984, pp. 110-113.
Wittmer et al., "Applications of ciN", Thin Solid Films 93 (1982), 397-405.
DeLaMoneda, "Self-Aligned Silicide Based Contacts", IBM Tech. Disc. Bull, 24(7A), Dec. 1981, pp. 3454-3457.
Wolf, et al., Silicon Processing, Lattice Press, 1986, pp. 554-565.
Tsukamoto, K., et al. "Self Aligned Titanium . . . " 2419 Japanese J. App. Phys. Supp., Aug. 30-Sep. 1, 1984, pp. 47-50.
Tsukamoto, K., et al. "Self-Aligned Titanium . . . " IEDM Technical Digest, 1984, pp. 130-133.
Yamamoto et al., "Effects of Impurities on Molybdenum and Polycrystalline Silicon Reaction," Denshi Tsushin Gakkai (Dec. 1982) pp. 39-45.
Michael E. Alperin, et al., "Development of the Self-Aligned Titanium Silicide Process for VLSI Applications", IEEE, Feb. 1985, vol. ED-32, No. 2, pp. 141-149.
C. Y. Ting, "TiN Formed By Evaporation as a Diffusion Barrier Between Al and Si", J. Vac. Sci. Technol. 21(1), May/Jun. 1982 pp. 14-18.
Ting, "Silicide for Contacts and Interconnects", IEDM 84, pp. 110-113.
Tsang, "Forming Thick Metal Silicide for Contact Barrier", IBM Technical Disclosure, vol. 19, No. 9, Feb. 1977, pp. 3383-3385.
D. C. Chen, et al., "A New Device Interconnect Scheme for Sub-Micron VLSI", IEDM Technical Digest, San Francisco, Calif. Dec. 1984, pp. 118-121.
V. L. Rideout, "Method of Fabricating MOSFET Integrated Circuits with Low Resistivity Interconnection Lines", IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, pp. 2563-2566.

Affiliated with

Also associated with

Rating

VLSI interconnect method and structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with VLSI interconnect method and structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and VLSI interconnect method and structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2098346