Predictive capacitance layout method for integrated circuits

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364490, 364489, 364488, G06F 1750

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active

RE0356719

ABSTRACT:
A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.

REFERENCES:
patent: 4263651 (1981-04-01), Donath et al.
patent: 4615011 (1986-09-01), Linsker
patent: 4694403 (1987-09-01), Nomura
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4701860 (1987-10-01), Mader
patent: 4823278 (1989-04-01), Kikuchi et al.
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 4896272 (1990-01-01), Kurosawa
patent: 4924430 (1990-05-01), Zasio et al.
patent: 4947365 (1990-08-01), Masubuchi
patent: 4967367 (1990-10-01), Piednoir
patent: 5029102 (1991-07-01), Drumm et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5095454 (1992-03-01), Huang
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5164907 (1992-11-01), Yabe
patent: 5191541 (1993-03-01), Landman et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5235521 (1993-08-01), Johnson et al.
patent: 5262959 (1993-11-01), Chkoreff
patent: 5274568 (1993-12-01), Blinne et al.
patent: 5278769 (1994-01-01), Bair et al.
patent: 5282148 (1994-01-01), Poirot et al.
patent: 5287289 (1994-02-01), Kageyama et al.
patent: 5293327 (1994-03-01), Ikeda et al.
patent: 5353433 (1994-10-01), Sherman
patent: 5406497 (1995-04-01), Altheimer et al.
patent: 5459673 (1995-10-01), Carmean et al.
patent: 5519631 (1996-05-01), Nishioka et al.
"Analytical Power/Timing Optimization Technique for Digital System" by Ruehli et al., IEEE 14th Design Automation Conf., 1977, pp. 142-146.
"Circuit Placement for Predicatable Performance" by Hauge et al., IEEE International Conf. on Computer Aided Design, ICCAD-87, pp. 88-91, 1987.

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