Substrate bias generator for semiconductor devices

Details Substrate bias generator for semiconductor devices Substrate bias generator for semiconductor devices

1991-06-25

1992-12-15

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072961, 3072968, 3072966, H03K 301

Patent

active

051720132

ABSTRACT:
A substrate bias generator for supplying a predetermined substrate bias voltage to a semiconductor device includes a charge circuit in which there is provided a rectifying pMOS transistor formed in an n-well. The n-well is maintained at a negative voltage level during the pumping operation. As a result, the threshold voltage of the rectifying pMOS transistor is prevented from increasing to enable the bias volatge to be supplied at a higher efficiency.

REFERENCES:
patent: 4471290 (1984-09-01), Yamaguchi
patent: 4794278 (1988-12-01), Vajdic
patent: 4843256 (1989-06-01), Scade et al.
patent: 4920280 (1990-04-01), Cho et al.
patent: 4961007 (1990-10-01), Kumanoya et al.
patent: 5041739 (1991-08-01), Goto

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