Integrated semiconductor memory

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365201, G06F 1110

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active

047681942

ABSTRACT:
An integrated semiconductor memory includes n identical memory cell fields, n.m data lines for writing memory data into and reading memory data out of the fields, m data input terminals receiving the memory data to be written into the semiconductor memory during writing, m first data switches for applying the memory data to a respective one of the n data lines as a function of addressing data, m second data switches each selecting a respective one of the n data lines when reading out the memory data applied to the n data lines as a function of the addressing data, an evaluation circuit connected to n of the n.m data lines in parallel to the second data switches issuing an output signal containing the memory data read out from the fields if none of the memory data are defective and having a high-resistance state if between 1 and n-1 memory data are defective, a third data switch transferring the memory data in parallel to all of the n data lines as a function of a control signal from a terminal, and m fourth data switches receiving the control signal and another control signal complementary thereto for feeding the memory data selected by the second data switch or the output signal from the evaluation circuit to a data output terminal, the data output terminal having a high-resistance state when the output signal from the evaluation circuit has a high-resistance state.

REFERENCES:
patent: 4458338 (1984-07-01), Giebel et al.
patent: 4625162 (1986-11-01), Bosnyak
patent: 4625311 (1986-11-01), Fitzpatrick
patent: 4654827 (1987-03-01), Childers
patent: 4686456 (1987-08-01), Furuyama
patent: 4692923 (1987-09-01), Poeppelman
IEEE International Solid-State Circuit Conference, 1981, pp. 84 to 85.
Elektronik, No. 15, Jul. 30, 1982, pp. 27 to 30.
Patents Abstract of Japan, vol. 6, (P-111)[940], Apr. 21, 1982.

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