Method for making planar vertical channel DMOS structures

Details Method for making planar vertical channel DMOS structures Method for making planar vertical channel DMOS structures

1986-03-24

1988-08-30

Ozaki, George T.

Fishing, trapping, and vermin destroying

437913, 357 234, H01L 2138, H01L 21425

Patent

active

047677228

ABSTRACT:
A DMOS power transistor has a vertical gate and a planar top surface. A vertical gate fills a rectangular groove lined with a dielectric material which extends downward so that source and body regions lie on each side of the dielectric groove. Carriers flow vertically between source and body regions and the structure has a flat surface for all masking steps.

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