Method and apparatus for testing a network with a programmable l

Details Method and apparatus for testing a network with a programmable l Method and apparatus for testing a network with a programmable l

1994-11-28

1998-02-10

Beausoliel, Jr., Robert W.

Excavating

371 225, G01R 3128

Patent

active

057176981

ABSTRACT:
A circuit architecture for testing a programmable logic matrix, e.g., the PLA type, has a group of input latches and a corresponding group of output latches connected to the matrix, and test information paths structured with at least one data bus and one address bus. The input latch and the output latch are connected electrically to the test data bus and to the test address bus to allow matrix testing with considerable time saving over known circuitry.

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IEEE Intercon Conference Record, vol. 17, May 12, 1992, New York US, pp. 271-276, Jones R. et al. "Sub-Micron CMOS gate arrays with IEEE 1149.1 JTAG".

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