Semiconductor memory device capable of high speed plural paralle

Details Semiconductor memory device capable of high speed plural paralle Semiconductor memory device capable of high speed plural paralle

1996-01-22

1998-02-10

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

365201, G11C 800

Patent

active

057176523

ABSTRACT:
A test mode control circuit detects designation of a test mode in accordance with a combination of external control signals and address signals, and activates an internal period setting circuit. Internal period setting circuit generates a clock signal having a prescribed period when activated, and applies it to a control circuit. In accordance with the test mode designating signal from test mode setting circuit and the clock signal from internal period setting circuit, control circuit causes an internal address generating circuit to generate an internal address signal successively in synchronization with the clock signal, so that a word line of a memory array is selected.

REFERENCES:
patent: 4984210 (1991-01-01), Kumanoya
patent: 4985868 (1991-01-01), Nakano
patent: 5343438 (1994-08-01), Choi
ISSCC94, "A Delay Line Loop for Frequency Synthesis of De-Showed Clock", Alex Walzman, pp. 298-299.
ISSCC94, "A 2.5V Delay-Locked Loop for an 18Mb 500MB/s DRAM", Thomas Lee et al, pp. 300-301.
ISSCC93, "PLL Design for a 500 MB/s Interface", Mark Holowitz, et al., pp. 160-161.
ISSCC89, "A 55ns 16Mb DRAM", Toshio Takeshima et al., pp. 246-247.
ISSCC92, "A 30ns 64Mb DRAM with Built-in Self-test and Repair Function", Hiroki Koike, et al., pp. 150-151.

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