Method of fabricating a silicon BJT

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 31, 437917, 148DIG96, H01L 21265

Patent

active

057168598

ABSTRACT:
A method of fabricating a bipolar junction transistor having emitter line spacings on the order of approximately 0.25 microns or less is disclosed. Windows are opened in the silicon dioxide layer for the emitter collector and base fabrication. A layer of silicon nitride is disposed on top of the layer of silicon dioxide having been deposited over he entire surface containing approximately 0.5 width line features at he emitter, base and collector sites. Silicon nitride is deposited by low pressure chemical vapor deposition (LPCVD). The deposited nitride film is etched using a standard reactive ion etching technique, removing the silicon nitride from the horizontal surfaces of the oxide without removing the nitride from the sidewalls of the etched opening at the emitter, base and collector sites. The result of the RIE etching is that the thickness of the film on the horizontal surfaces is removed without removal of the nitride from the sidewalls of the etched pattern. The resulting spacer produces the window of the original features at the emitter, base and collector by a dimension of approximately 2X the thickness of the deposited silicon nitride.

REFERENCES:
patent: 4210689 (1980-07-01), Komatsu
patent: 4315271 (1982-02-01), Roger
patent: 4381953 (1983-05-01), Ho et al.
patent: 4573256 (1986-03-01), Lechaton et al.
patent: 4617724 (1986-10-01), Yokoyama et al.
patent: 4679305 (1987-07-01), Morizuka
patent: 4750025 (1988-06-01), Chen et al.
patent: 4758870 (1988-07-01), Hase et al.
patent: 4803181 (1989-02-01), Buchmann et al.
patent: 4825265 (1989-04-01), Lunardi et al.
patent: 4923563 (1990-05-01), Lee
patent: 4957874 (1990-09-01), Soejima
patent: 4963501 (1990-10-01), Ryan et al.
patent: 4967254 (1990-10-01), Shimura
patent: 5017995 (1991-05-01), Soejima
patent: 5023203 (1991-06-01), Choi
patent: 5063167 (1991-11-01), Shimura
patent: 5066615 (1991-11-01), Brady et al.
patent: 5073512 (1991-12-01), Yoshino
patent: 5130272 (1992-07-01), Ferla et al.
patent: 5296410 (1994-03-01), Yang
patent: 5397731 (1995-03-01), Takemura
patent: 5516710 (1996-05-01), Boyd et al.
IBM Technical Disclosure Bulletin; Title: High-Performance Intrinsic Bipolar Translator; Date: Jul. 1993, pp. 479-482.
T.Aoyama, et al.; Title: Selective Polysilicon Deposition (SPD) by Hot-Wall LPCVD and Its Application to High Speed Bipolar Devices; Date: Unknown; pp. 665-668.
Self-Aligned ALGaAs/GaAs HBTs and 35 PS 1cml Ring Oscillators Fabricated by Mg and P Double Implantation; K. Morizuk, et al.; Extended Abstracts of the 18th (1986 International) Conference on Solid State Devices and Materials, Toykyo, 1986, pp. 359-362.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of fabricating a silicon BJT does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a silicon BJT, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a silicon BJT will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2076651

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.