Processor having a register configuration suited for parallel ex

Details Processor having a register configuration suited for parallel ex Processor having a register configuration suited for parallel ex

1997-09-19

1999-02-16

Shah, Alpesh M.

395393, G06F 1576

Patent

active

058729895

ABSTRACT:
A method and apparatus for handling a large-capacity register file by using a small instruction field as to support a software pipeline. The invention includes a register file having a plurality of physical registers corresponding to a plurality of physical register numbers and a converter which converts logical register numbers included in instructions to be executed into physical register numbers. A physical register, which is used when a logical register is accessed as a result of execution of an instruction, is specified by a pointer corresponding to the logical register number included in the instruction. The pointer used for the access is incremented if so specified in the instruction to ensure that subsequent instructions making access to the same logical register use different physical registers.

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Fujii et al, "A Register File Architecture for Instruction Level Prallel Processing and its Evaluation", 1993, Central Research Laboratory, Hitachi, Ltd., pp. 307 -314.

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