Electronically selectable redundant array (ESRA)

Details Electronically selectable redundant array (ESRA) Electronically selectable redundant array (ESRA)

1984-04-09

1986-04-08

Fleming, Michael R.

Excavating

371 10, G06F 1120

Patent

active

045817391

ABSTRACT:
The disclosure is directed to an electronically selectable redundant array or memory technique and circuitry. More particularly the invention utilizes Level Sensitive Scan Design (LSSD) circuitry with limited modification to perform the additional function of selecting a redundant word (or words) in a memory chip containing at least one defective word. The correction mechanism is independent of which word line (or word lines) is bad, and is therefore independent of I/O pin (or pad) connection of the array chip.

REFERENCES:
patent: 3222653 (1965-12-01), Rice
patent: 3434116 (1969-03-01), Anacker
patent: 3633175 (1972-01-01), Harper
patent: 3772652 (1973-11-01), Hilberg
patent: 3783254 (1974-01-01), Baxter
patent: 3845476 (1974-10-01), Boehm
patent: 3868646 (1975-02-01), Bergman
patent: 3898443 (1975-08-01), Smith
patent: 3992702 (1976-11-01), Bailey
patent: 3995261 (1976-11-01), Goldberg
patent: 4310901 (1982-01-01), Harding
patent: 4376300 (1983-03-01), Tsang
patent: 4412327 (1983-10-01), Fox
patent: 4429389 (1984-01-01), Cahiller
patent: 4450559 (1984-05-01), Bond
patent: 4460997 (1984-07-01), Harns
patent: 4460999 (1984-07-01), Schmidt
patent: 4475194 (1984-10-01), LaVallee et al.
patent: 4488298 (1984-12-01), Bond
patent: 4523313 (1985-06-01), Nibby
"Redundant Memory Cell and Decoder" by N. F. Brickman, IBM Technical Disclosure Bulletin, vol. 13, No. 7, Dec. 1970, p. 1924.
"Redundant Bit Line Decode Circuit" by S. E. Schuster, IBM Technical Disclosure Bulletin, vol. 14, No. 5, Oct. 1971, p. 1513.
"Redundant Bit Line Decode Circuit" by J. L. Chu et al., IBM Technical Disclosure Bulletin, vol. 18, No. 6, Nov. 1975, p. 1777.
"Redundancy Scheme for Array Chips" by F. Haist et al., IBM Technical Disclosure Bulletin, vol. 19, No. 3, Aug. 1976, p. 964.
"Memory System with High-Performance Word Redundancy" by B. F. Fitzgerald et al., IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, p. 1638.
"Address Skip-A Means for Utilizing Imperfect Storage" by F. E. Sakaley, IBM Technical Disclosure Bulletin, vol. 20, No. 5, Oct. 1977, p. 1841.
"Effective Scheme for Utilizing Partially Good Chips in Memory System" by G. G-C. Liu, IBM Technical Disclosure Bulletin, vol. 20, No. 8, Jan. 1978, p. 3009.
"Use of Partially Good Memory Chips" by R. F. Meyers et al., IBM Technical Disclosure Bulletin, vol. 21, No. 9, Feb. 1979, p. 3582.
"Module Personalization for Partially Good Chip Utilization" by R. Peters, IBM Technical Disclosure Bulletin, vol. 21, No. 11, Apr. 1979, p. 4535.
"Electronic Reorganization of Memory for Handling Uncorrectable Memory Errors" by A. V. Stays et al., IBM Technical Disclosure Bulletin, vol. 22, No. 12, May 1980, p. 5378.
"Redundancy Scheme for Embedded Arrays" by R. Brosch et al., IBM Technical Disclosure Bulletin, vol. 23, No. 1, Jun. 1980, p. 213.
"Semiconductor Memory Redundancy at the Module Level" by B. F. Fitzgerald et al., IBM Technical Disclosure Bulletin, vol. 23, No. 8, Jan. 1981, p. 3601.
"Storage Array with Bad Bit Bypass" by W. W. Wu, IBM Technical Disclosure Bulletin, vol. 23, No. 8, Jan. 1981, p. 3761.
"Redundant Circuit Personalization at the Module Level" by J. P. Coullahan et al., IBM Technical Disclosure Bulletin, vol. 23, No. 9, Feb. 1981, p. 4168.
"Passivation Process for Semiconductor Device with Fusible Link Redundancy" by D. E. Davis et al., IBM Technical Disclosure Bulletin, vol. 23, No. 10, Mar. 1981, p. 4451.
"Redundancy Programming with Threshold Shift" by B. F. Fitzgerald et al., IBM Technical Disclosure Bulletin, vol. 24, No. 7B, Dec. 1981, p. 3809.
"Memory Data Steering On-Chip Switching and Off-Chip Control Network" by J. R. Cavaliere et al., IBM Technical Disclosure Bulletin, vol. 24, No. 9, Feb. 1982, p. 4779.
"Dynamic Allocation of Redundant Memory Components" by F. J. Aichelmann et al., IBM Technical Disclosure Bulletin, vol. 24, No. 9, Feb. 1982, p. 4776.
"Dynamic Selection of Partial Good Array Chips by Bit Address Selection" by L. J. Bosch et al., IBM Technical Disclosure Bulletin, vol. 25, No. 3B, Aug. 1982, p. 1485.

Affiliated with

Also associated with

Rating

Electronically selectable redundant array (ESRA) does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronically selectable redundant array (ESRA), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronically selectable redundant array (ESRA) will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2069897