Patent
1995-12-19
1998-04-21
Kim, Kenneth S.
395569, 395678, G06F 940
Patent
active
057428220
ABSTRACT:
A multithreaded processor includes an instruction pipelined unit 140 and a register file 120 composed of a plurality of register banks 130. The register file 120 is coupled to an external memory 190 through register frame load/store lines 121, so that a register frame, which is defined as a content stored in one register bank 130, can be loaded and stored in bundle. When a thread parallel start instruction and a thread sequential start instruction are executed, the register frames are saved through the load/store lines 121. When a thread end instruction and a thread return instruction are executed, the register frames are restored through the load/store lines 121.
REFERENCES:
patent: 5050067 (1991-09-01), McLagan et al.
patent: 5165038 (1992-11-01), Beard et al.
patent: 5339415 (1994-08-01), Strout, II et al.
patent: 5353418 (1994-10-01), Nikhil et al.
patent: 5404469 (1995-04-01), Chung et al.
19th Annual Intl. Symposium on Computer Architecture, Gold Coast, Queensland, Australia, 19-21 May, 1992, vol. 20, No. 2, ISSN 0163-5964, Computer Architecture News, May 1992, pp. 156-167, R.S. Nikhil, et al., "A Multithreaded Massively Parallel Architecture".
Kim Kenneth S.
NEC Corporation
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