Backside exposure of desired nodes in a multi-layer integrated c

Details Backside exposure of desired nodes in a multi-layer integrated c Backside exposure of desired nodes in a multi-layer integrated c

1998-09-04

2000-11-14

Lam, Cathy F.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257 48, 257692, 257686, 257748, 438 18, H01L 23053

Patent

active

061473995

ABSTRACT:
Aspects for exposing local areas for desired nodes in a multi-layer integrated circuit from the backside are described. In an exemplary method aspect, the method includes removing a predetermined portion of a first backside layer, opening chosen local areas with focused ion beam etching through at least the first backside layer, and exposing a desired node in a metal layer lower than the first backside layer with reactive ion etching. The method further includes removing the predetermined portion by performing reactive ion etching to a predetermined stop point. Alternatively, the first backside layer is mechanically polished to a predetermined thickness. Additionally, the method includes utilizing a high current ion beam during the focused ion beam etching.

REFERENCES:
patent: 5767578 (1998-06-01), Chang et al.
patent: 5990562 (1999-11-01), Vallett

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