Hardware reset of a write state machine for flash memory

Details Hardware reset of a write state machine for flash memory Hardware reset of a write state machine for flash memory

1995-04-10

1998-04-21

Swann, Tod R.

395481, G06F 1200

Patent

active

057427879

ABSTRACT:
A method of quickly aborting an automated program or erase sequence on a nonvolatile memory array in which each operation of the sequence is performed by a write state machine. During each operation of the program or erase sequence, the state of an abort signal is detected to determine whether or not the sequence should be aborted. If the abort signal is in a second state, the sequence continues to the next operation. If the abort signal is in a first state, the write state machine aborts the sequence and the nonvolatile memory array is placed in a read-only mode. The nonvolatile memory array is then available for user access.

REFERENCES:
patent: 5287469 (1994-02-01), Tsuboi
patent: 5351216 (1994-09-01), Salt
patent: 5414829 (1995-05-01), Fandrich
patent: 5509134 (1996-04-01), Fandrich

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