Excavating
Patent
1996-06-20
1998-04-21
Beausoliel, Jr., Robert W.
Excavating
365201, G01R 3128
Patent
active
057426155
ABSTRACT:
In order to shorten initialization time, a flash type non-volatile semiconductor memory of the invention comprises a line decoder (2) for selecting all of word lines (WL1 to WLm), a word line voltage generator (3) for generating various voltage, a column decoder (4) for selecting or not selecting all of digit lines (DL1 to DLn).
Erase pulse impression process is performed by supplying a positive first word line voltage to all the word lines (WL1 to WLm) selected, and an erase voltage (Vs) to a source line, leaving all the digit line floating. All of memory-cell-transistors (MC11 to MCmn) are erased by infusing hot carriers in their floating gates by way of avalanche breakdown caused between their sources and substrates.
Depression discrimination is performed with a sense amplifier (8) by selecting all digit lines (DL1 to DLn) and supplying all word lines (WL1 to WLm) with a second word line voltage.
REFERENCES:
patent: 5109257 (1992-04-01), Kondo
patent: 5521864 (1996-05-01), Kobayashi et al.
patent: 5544117 (1996-08-01), Nakayama et al.
patent: 5554868 (1996-09-01), Hayashikoshi et al.
patent: 5572463 (1996-11-01), Akaogi et al.
Kondo Ichiro
Tanaka Nobuyuki
Beausoliel, Jr. Robert W.
Iqbal Nadeem
NEC Corporation
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