Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Patent
1998-11-18
2000-11-14
Bowers, Charles
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
438396, 438239, 438592, 438240, H01L 2120, H01L 218242, H01L 214763
Patent
active
061469602
ABSTRACT:
A method of forming mixed mode devices is provided. A field oxide layer is formed on the substrate to isolate active regions from each other. A gate oxide layer is formed on the substrate, positioned over the active regions. A first conductive layer, a silicide layer and a second conductive layer are formed on the field oxide layer and on the gate oxide layer. The second conductive layer is converted to an oxide layer as a dielectric layer of a capacitor by thermal oxidation. A third conductive layer is formed and defined on the dielectric layer to form an upper electrode of the capacitor. A anisotropic etching step is performed to remove a part of the dielectric layer, a part of the silicide layer and a part of the first conductive layer to complete the capacitor and to form a gate of a transistor.
REFERENCES:
patent: 5804488 (1998-09-01), Shih et al.
patent: 6033950 (1998-09-01), Chen et al.
Bowers Charles
Huynh Yennhu B.
United Microelectronics Corp.
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