Permutating analog shift register variable delay system

Details Permutating analog shift register variable delay system Permutating analog shift register variable delay system

1979-06-18

1981-05-12

Farley, Richard A.

Communications, electrical: acoustic wave systems and devices

Acoustic image conversion

With memory means

333165, 128660, 73609, 73626, 367103, G01S 1589

Patent

active

042675847

ABSTRACT:
A dynamically variable electronic delay line for real time ultrasonic imaging systems is disclosed which controllably phases the signals associated with an array of electromechanical transducer elements and thereby enables selective scanning and dynamic focusing of a target. A controllable variable electronic time delay apparatus is coupled to each of the electromechanical transducer elements of the array having separate write-in and read-out addressing capabilities. The signals associated with a respective ultrasonic transducer element are fed in at selected write-in addresses and subsequently read-out and extracted after an initial time delay interval. The write-in and read-out address pointers of the memory system are continuously sequenced during operation of the device and the time delay interval is a function of the difference between the addresses and the clock rate. The initial delay can be varied instantaneously by modifying either the write-in or the read-out address pointer during the sequencing thereof, such modification being defined as an "edit-splice" technique. In the preferred embodiments of the invention, the time delay apparatus comprises a trio of analog shift register memories of the charge coupled device (CCD) type for each transducer section together with commutating write and read means. Both the write and read means for each CCD trio are independently controllable for use in an "edit-splice" imaging system.

REFERENCES:
patent: 4058003 (1977-11-01), Macovski

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