Memory address designating system

Details Memory address designating system Memory address designating system

1979-03-05

1981-05-12

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 936

Patent

active

042675812

ABSTRACT:
A memory address designating system comprising a program counter and data counter for holding the addresses of an instruction word area and data area respectively of a memory, an increment/decrement counter for modifying the address, and gate circuits for controlling data transfer between the program counter, data counter and increment/decrement counter, in which, when the memory is accessed by the addresses of the instruction word area and data area of the memory, an address held in the program counter is modified by an increment/decrement counter and consequently is incremented by one and sent through a gate to the data counter where it is held. On the other hand, the address of the data area held in the data counter is supplied through a gate to he program counter and then to the increment/decrement counter where it is modified. At the same time, the data of the data area of the memory is fetched and the modified address is supplied to the data counter while the modified address stored in the data counter is supplied to the program counter.

REFERENCES:
patent: 3299261 (1967-01-01), Steigerwalt, Jr.
patent: 3978454 (1976-08-01), Willard
patent: 4021781 (1977-05-01), Caudel
patent: 4031514 (1977-06-01), Kihara
patent: 4073006 (1978-02-01), Tubbs

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