Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Patent
1999-02-25
2000-07-18
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
712218, G06F 938
Patent
active
060921773
ABSTRACT:
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.
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Coleman Eric
Tandem Computers Incorporated
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