Method of pipelining sequential writes in a flash memory

Details Method of pipelining sequential writes in a flash memory Method of pipelining sequential writes in a flash memory

1993-06-30

1996-05-21

Kim, Matthew M.

Boots, shoes, and leggings

395428, 364DIG1, 364DIG2, 36518533, G06F 1200, G11C 1700, G11C 800

Patent

active

055198473

ABSTRACT:
A method of increasing the data throughput of a memory device including a page buffer. Data throughput is increased by pipelining write operations such that one plane of the page buffer is being used to program the memory array of the device while the other plane of the page buffer is being loaded with data to be used in the next program operation. The first write operation is set up by loading a first block of data in to the first plane of the page buffer. In the following clock cycle, the first operation begins by commanding the memory device to program the memory array with the first block of data stored in the first plane. The second write operation is setup immediately following the first command to program. The second write operation is setup by loading a second block of data into the second plane of the page buffer. Loading of the second plane occurs while the memory array is being programmed from the first plane. The second write operation begins by commanding the array controller to program the flash memory array with the second block of data stored in the second plane.

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John L. Hennessy and David A. Patterson, Computer Architecture a Quantitative Approach, pp. 251-257 (Morgan Kaufman Publishers, Inc. 1990).

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