Full-speed microprocessor testing employing boundary scan

Details Full-speed microprocessor testing employing boundary scan Full-speed microprocessor testing employing boundary scan

1995-01-27

1996-05-21

Canney, Vincent P.

Excavating

39518306, H04B 1700

Patent

active

055197159

ABSTRACT:
A method is disclosed for loading a compiled test program into a microprocessor's internal caches and then controlling the execution of that program. Initially, the microprocessor's internal clock is disabled. Then for each memory location specified in the compiled program, the memory content associated with that location is loaded into the appropriate microprocessor cache. This is accomplished in two primary steps. First, the memory content is shifted into positions on the pins of the microprocessor by a boundary scan shift operation via an IEEE 1149.1 interface. Second, after the pins have the appropriate bit values for the current memory content, an external clock supplies the microprocessor with clock cycles that are then used by the microprocessor to control the loading of data/instructions from the pins into the appropriate data or instruction cache. The process of loading the pins with data via boundary scan, and then shifting the data into appropriate caches is repeated for each memory content of the compiled program until all instructions in the program have been loaded into the appropriate caches. Thereafter, the microprocessor is forced into normal execution mode by resetting the microprocessor to reenable its internal clock. Finally, the test program is executed in a manner that allows a user to interact with the microprocessor during execution.

REFERENCES:
patent: 5426650 (1995-06-01), Ganapathy et al.
patent: 5434804 (1995-07-01), Bock et al.
"IEEE Standard Test Access Port and Boundary-Scan Architecture," vol. IEEE Standard 1149.1-1990.

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