Variable symmetry multiphase clock generator

Details Variable symmetry multiphase clock generator Variable symmetry multiphase clock generator

1978-03-29

1980-03-04

Nusbaum, Mark E.

Boots, shoes, and leggings

328 62, 307269, G06F 104

Patent

active

041919980

ABSTRACT:
The clock generator, which is shown as being a part of a data processor, includes a recirculating shift register and gate combination for deriving a set of four clock phase signals from a master clock signal. The generator also includes two gates and a D flop which form sequential circuitry. The latter controls the shift register to impart a desired nonsymmetry to the clock signals, and to vary that symmetry, as necessary to minimize the clock cycle time and to maximize the processor operating speed. To this end, the circuitry normally makes the clock pulse widths a minimum, consistent with the processor requirements, and, on demand, doubles the widths of only those clock pulses which are actually timing the slowest processor portion, thereby lengthening only those specific clock cycles which contain the demanded widened clock pulses.

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D. McGlynn, "Microprocessors Technology, Architecture, and Applications", publ. John Wiley & Sons, pp. 120, 122.

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