Method to reduce breakage of V-grooved <100> silicon subst

Details Method to reduce breakage of V-grooved <100> silicon subst Method to reduce breakage of V-grooved <100> silicon subst

Filed on

1978-11-13

Date issued

1980-03-04

Examiner

Smith, John D.

Patent Class

Coating processes

SubClass

Electrical product produced

SubSubClass

Condenser or capacitor

Other Related Categories

148 332, 156662, 357 52, 357 54, 357 55, 427 86, 427 95, 427355, H01L 21461

Type

Patent

Status

active

Patent number

041917880

Description

ABSTRACT:
Flat and parallel depositions of low pressure chemical vapor deposited (LPCVD) polycrystalline intrinsic silicon are formed on both sides of a wafer of P-I-N <100> V-grooved substrate of silicon to support the wafer during subsequent polish removal from the top surface. This structurally reinforces the crystal wafer and helps prevent warpage and cracking during subsequent handling.

REFERENCES:
patent: 3699644 (1972-10-01), Cocca
patent: 3806771 (1974-04-01), Petruzella
patent: 3859127 (1975-01-01), Lehner
patent: 3911562 (1975-10-01), Youmans
patent: 3969168 (1976-07-01), Kuhn
patent: 4014037 (1977-03-01), Matsushita et al.
patent: 4053335 (1977-10-01), Hu
patent: 4086613 (1978-04-01), Biet et al.

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